1. Field of the Invention
The present invention is generally directed to the processing of audio signals. In particular, the present invention is directed to sampling rate conversion (SRC) of audio signals.
2. Background
In some conventional audio processors, sampling rate conversion (SRC) is achieved by using a simple linear interpolation algorithm implemented in dedicated hardware. Conceptually, this algorithm is equivalent to drawing a straight line between each pair of adjacent samples of an input digital audio signal to approximate an underlying continuous-time analog signal, and then re-sampling the resulting piecewise-linear signal at a target output sampling rate. Although this algorithm has a very low complexity and is quite simple to implement, it suffers from poor audio quality, especially when upsampling from a very low sampling rate such as 8 kHz, to a much higher sampling rate such as 48 kHz. There is a very loud “image” distortion in the output of such a system.
Improved audio quality can be achieved by implementing known SRC methods that require high computational complexity, large memory size, or both. However, the use of such methods may be impossible in a system having limited processing resources and/or silicon area. For example, a typical DSP-textbook approach to SRC is to upsample an input audio signal by an integer factor of L, then downsample by an integer factor of M, in order to achieve an output sampling rate that is L/M times the input sampling rate. However, this approach results in unacceptably high complexity if one tries to convert, for example, 8 kHz to 44.1 kHz, because the simplest ratio of integers would be 441/80 in this case. Other conventional SRC algorithms can provide a significant improvement as compared to linear interpolation, but still produce audible image distortion and are also fairly complex.
What is desired, then, is a low-complexity SRC algorithm that provides a significant improvement in audio quality as compared to known low-complexity approaches, such as simple linear interpolation. The desired SRC algorithm should be simple to implement in hardware, requiring relatively few gates and thus permitting a reduced silicon area.